ContributorQuestion about Autonomous Mode Configuration
Hi
We use A10 10AX057H3F34E2SG for both PCIe GEN3.0 connected with host PC. To circumvent PCIe 100ms wake up time requirement, we may use Autonomous Mode for A10 FPGA Configuration. Some questions here.
In UG-01145_avmm intel doc, chapter 12 mentioned CvP and Autonomous Mode (AM). Both of these two means takes similar thought that split traditional bits-stream files into two parts, firstly Peripheral Image (contains PCIe Hard IP) anf Core Fabric Image. Smaller Peripheral Image are firstly configured so that Host PC could start PCIe link training within 100ms.
(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf)
We found some dedicated user guide on CvP topics such as (ug-20010), but we plan to use AM as CvP is not applicable to our situation. However, I do not found any doc about AM except UG-01145_avmm(rather simple although). Where could I found detailed info about AM, such as bit-stream sizes of two parts in AM, timing info, hardware design constrains?
Further more, UG-01145_avmm section 12.2 indeed mentioned that “ALL PCIe IP cores on a device can operate in autonomous mode. However, only the bottom Hard IP for PCI Express on either side can satisfy the 100 ms PCIe wake up time requirement.” So what is the exact context of this “BOTTM”? Under TOP VIEW or Bottom VIEW? And you know, sometimes “BOTTOM side” could become “TOP side” if chips are spined/rotated……
- Hi, Please refer to chapter 4.2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf document. It will mention which PCIe hard IP will be able to meet the 100ms wake up time. Based on that location then you will need to either mapped it to the pin planner or pin-out file for the exact pin to be connected to the PCIe host.
