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ContributorQuestion about Autonomous Mode Configuration
- Hi, Please refer to chapter 4.2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf document. It will mention which PCIe hard IP will be able to meet the 100ms wake up time. Based on that location then you will need to either mapped it to the pin planner or pin-out file for the exact pin to be connected to the PCIe host.
ContributorCopied from this link: https://forums.intel.com/s/question/0D50P00003yyPwwSAE/cvp-initialization-vs-update-modes-in-cyclone-v
hi , recently I had a same hard time with yours. After struggled in intel's docs, I do found something useful to solve our problem. See this Autonoumous Mode. It is different from CVP and it exactly answered your question "What I need is to have the periphery (Hard IP) image and core image load from on-board flash (AS x4 mode), with the Hard IP PCIe controller meeting the PCIe wake up time". just search "Autonoumous" in following docs. Hope it helps.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01110_avmm-1.7.pdf?wapkw=ug+01101
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-cvp-15.1.pdf?wapkw=ug+01101
Another point, if you want to use CVP, you will need software driver programs on Host PC. Intel provide driver demos for Linux, but no support for x86 OS.
