Forum Discussion
xytech
Contributor
ContributorQuestion about Autonomous Mode Configuration
Hi We use A10 10AX057H3F34E2SG for both PCIe GEN3.0 connected with host PC. To circumvent PCIe 100ms wake up time requirement, we may use Autonomous Mode for A10 FPGA Configuration. Some questions h...
- Hi, Please refer to chapter 4.2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf document. It will mention which PCIe hard IP will be able to meet the 100ms wake up time. Based on that location then you will need to either mapped it to the pin planner or pin-out file for the exact pin to be connected to the PCIe host.
JohnT_Altera
Regular Contributor
Regular ContributorHi,
Please refer to chapter 4.2 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf document. It will mention which PCIe hard IP will be able to meet the 100ms wake up time. Based on that location then you will need to either mapped it to the pin planner or pin-out file for the exact pin to be connected to the PCIe host.
xytechHi John, Thanks for answer. almost clear. Great!
I still have one question. On section4.2 , it mentioned a limitation that : "Intel Arria 10 devices do not support configurations that configure a bottom (left or right) hard IP block with a Gen3 x4 or Gen3 x8 IP core and also configure the top hard IP block on the same side with a Gen3 x1 or Gen3 x2 IP core variation." and then shows some channels examples for ONLY GT device with 72/96/48 XCVRs, figure16-18 .
Our GX device (10AX057H3F34E2SG ) contains two Hard PCIe IP, one bottom and one top. Does this limitation also applicable to our device?
I think it does, but need confirm from Intel.
Thanks again!
