Forum Discussion

xytech's avatar
xytech
Icon for Contributor rankContributor
7 years ago
Solved

Question about Autonomous Mode Configuration

Hi We use A10 10AX057H3F34E2SG for both PCIe GEN3.0 connected with host PC. To circumvent PCIe 100ms wake up time requirement, we may use Autonomous Mode for A10 FPGA Configuration. Some questions h...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi, You can get further information from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf. The bitstream will be the same as full bitstream size. Timing and hardware design constrains will follow PCIe specification. The full bitstream will contain both periphery and core design where it will configured the periphery bitstream 1st before continue with core bitstream. So once the periphery bitstream is completed then the PCIe link training can start.
xytech's avatar
xytech
Icon for Contributor rankContributor
7 years ago

Hi John, Thanks for reply.

I do searched through and compare ug_a10_pcie_avst.pdf and ug_a10_pcie_avmm.pdf (the one you mentioned), both docs are nearly the same. first doc on section 12.2, and second doc on section 14.2.

Thanks for point out that total bitstream size will not change. However, what I need to konw is the individual size of each part when use AM, that is, what's the size of periphery image? and what's the size of core image. Two

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

Furthermore, could you please take a look at my second question? Copied here.

Both docs mentioned “only the bottom Hard IP for PCI Express on either side can satisfy the 100 ms PCIe wake up time requirement.” What is the exact context of this “BOTTM” means? Under TOP VIEW or Bottom VIEW? on what position should the pin A1 be? As you know, sometimes “BOTTOM side” could become “TOP side” if chips are spined or flipped on PCB layout……

Thanks again.