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Kevin26's avatar
Kevin26
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2 years ago

Questa showing red signal when both signals from an AND operation are high

I am simulating a Platform Designer Cyclone 10 LP NIOS V system in Questa Starter Edition. After generating and modifying the testbench, I run the simulation in Questa. The simulation runs smoothly until a write to my Hyberbus controller IP. My Hyperbus controller IP has an AXI4 interface. During AXI write, a w_en signal goes high when the AXI_WVALID and AXI_WREADY signals are high. However, when this occurs, the w_en signal goes red in Questa and I am not sure why. Neither input is red and I'm not sure what else could make it go red. The waveforms and associated verilog code is attached. Can anyone share a possible reason for why the w_en signal goes red and what I can do about it?

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4 Replies

  • _AK6DN_'s avatar
    _AK6DN_
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    The w_en signal is not going high, it is going to undefined.

    I suspect there are other driver(s) that also assign to w_en that are driving low.

    When you drive both high and low you get an undefined, which is what you are seeing in the red trace.

    • Kevin26's avatar
      Kevin26
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      2 years ago

      That's the first thing I checked. I didn't mentioned this but I have simulated the Hyperbus controller IP by itself in Questa and it doesn't have this issue. It's only a problem when a simulate it with the entire platform designer system using the generated testbench. I have verified that there is nothing different in the verilog file containing the w_en signal in the generated testbench.

      • Kevin26's avatar
        Kevin26
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        2 years ago

        Never mind, I was looking at the wrong AXI verilog file. There was another file with a very similiar name that also had a w_en signal. Thanks for your help.

  • Kevin26's avatar
    Kevin26
    Icon for New Contributor rankNew Contributor
    2 years ago

    Just to close the loop on this issue. Once I was looking at the right file, I found that one of my input signals (AXI_WID) was uninitialized. The HDL generation process sometimes does not initialize unused signals. The NIOS V does not use the AXI WID signals and the HDL generator did not initialize WID to zero through the interconnect. The HDL generator did initialize all the other unused AXI signals but not WID. The w_en signal assignment is as follows in the correct file.

    assign w_en = AXI_WVALID & AXI_WREADY & (AXI_WID==wready_id);

    This is what led to the w_en signal turning red.