New Contributor
Frequent ContributorThe w_en signal is not going high, it is going to undefined.
I suspect there are other driver(s) that also assign to w_en that are driving low.
When you drive both high and low you get an undefined, which is what you are seeing in the red trace.
New ContributorThat's the first thing I checked. I didn't mentioned this but I have simulated the Hyperbus controller IP by itself in Questa and it doesn't have this issue. It's only a problem when a simulate it with the entire platform designer system using the generated testbench. I have verified that there is nothing different in the verilog file containing the w_en signal in the generated testbench.
New ContributorNever mind, I was looking at the wrong AXI verilog file. There was another file with a very similiar name that also had a w_en signal. Thanks for your help.
