Questa showing red signal when both signals from an AND operation are high

Just to close the loop on this issue. Once I was looking at the right file, I found that one of my input signals (AXI_WID) was uninitialized. The HDL generation process sometimes does not initialize unused signals. The NIOS V does not use the AXI WID signals and the HDL generator did not initialize WID to zero through the interconnect. The HDL generator did initialize all the other unused AXI signals but not WID. The w_en signal assignment is as follows in the correct file.

assign w_en = AXI_WVALID & AXI_WREADY & (AXI_WID==wready_id);

This is what led to the w_en signal turning red.