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Kevin26's avatar
Kevin26
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2 years ago

Questa showing red signal when both signals from an AND operation are high

I am simulating a Platform Designer Cyclone 10 LP NIOS V system in Questa Starter Edition. After generating and modifying the testbench, I run the simulation in Questa. The simulation runs smoothly...
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Kevin26's avatar
Kevin26
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2 years ago

That's the first thing I checked. I didn't mentioned this but I have simulated the Hyperbus controller IP by itself in Questa and it doesn't have this issue. It's only a problem when a simulate it with the entire platform designer system using the generated testbench. I have verified that there is nothing different in the verilog file containing the w_en signal in the generated testbench.

Kevin26's avatar
Kevin26
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2 years ago

Never mind, I was looking at the wrong AXI verilog file. There was another file with a very similiar name that also had a w_en signal. Thanks for your help.