Query for unused IO pins termination

--- Quote Start ---

I would offer to connect some clk input pins to the clock source. Even if those clock input pins are connected together.

--- Quote End ---

Good point. I took as granted, that some (at least one) clock pins are connected.

With CIII, you have the option to route global clocks across the chip, accepting some additional uncertainty and jitter, or supply up to four quadrants by dedicated clock pins. The latter is unpleasant with economic (e.g. 4 layer) PCBs, so I mostly choose the first one. With previous FPGA series, global clock routing wasn't available.

Thanks for quick response.

It means that I don't need to hardwire the unused pins of the FPGA chip to GND or VCC on PCB, right?

In my design, I have configured two clock inputs on FPGA chip for 50Mhz system clock. Other unused clk inputs GNDed on PCB.

And for all other unused pins I will set to "input with weak pull-up" in Quartus II software setting.

Enlighten me with this design if any wrong steps.

Thanks a lot.

An advice:

In Quartus, create an empty design with the signals that you have connected to the FPGA, perform the pin assignment and compile the design.

In addition, once the design has been compiled, Quartus will produce the .pin text file describing each pin.

Double check your PCB design against the contents of that file and against the Cyclone III's pin connection guidelines.

HI,

Thanks for every response.

I have checked my project's .pin file.

It describes all unused clok input pins to GND+.

That means I have to connect all those pins to system GND manually(i.e. externally).

Now I got the compelete idea.

Thanks once again.