Query for unused IO pins termination

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I would offer to connect some clk input pins to the clock source. Even if those clock input pins are connected together.

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Good point. I took as granted, that some (at least one) clock pins are connected.

With CIII, you have the option to route global clocks across the chip, accepting some additional uncertainty and jitter, or supply up to four quadrants by dedicated clock pins. The latter is unpleasant with economic (e.g. 4 layer) PCBs, so I mostly choose the first one. With previous FPGA series, global clock routing wasn't available.