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Altera_Forum
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15 years ago

Query for unused IO pins termination

Hi, I am trying to design a development board with EP3c25U256C8N - a cyclone iii FPGA. I have some confusion regarding how to treat the various unused pins in the design of FPGA chip. I have ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

On the other hand, I would offer to connect some clk input pins to the clock source. Even if those clock input pins are connected together. Check the global clock networks in datasheet.