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Altera_Forum
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14 years ago

Query for unused IO pins termination

Hi, I am trying to design a development board with EP3c25U256C8N - a cyclone iii FPGA. I have some confusion regarding how to treat the various unused pins in the design of FPGA chip. I have ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for quick response.

It means that I don't need to hardwire the unused pins of the FPGA chip to GND or VCC on PCB, right?

In my design, I have configured two clock inputs on FPGA chip for 50Mhz system clock. Other unused clk inputs GNDed on PCB.

And for all other unused pins I will set to "input with weak pull-up" in Quartus II software setting.

Enlighten me with this design if any wrong steps.

Thanks a lot.