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Altera_Forum
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14 years ago

Query for unused IO pins termination

Hi, I am trying to design a development board with EP3c25U256C8N - a cyclone iii FPGA. I have some confusion regarding how to treat the various unused pins in the design of FPGA chip. I have ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

HI,

Thanks for every response.

I have checked my project's .pin file.

It describes all unused clok input pins to GND+.

That means I have to connect all those pins to system GND manually(i.e. externally).

Now I got the compelete idea.

Thanks once again.