Honored Contributormy design has wide adders, 42 bit adders. with 10ns clock period, it has -10ns slack. I change the adder path to be multicycle path x2.
with data required time being 20ns, the new Quartus compile result is -13ns violations. it seems to me it does not make sense. can someone shed some light on this?
Honored ContributorDid you add a multicycle -hold 1 to the same path? Without that, you're telling Quartus the datapath must be greater than 10ns. With the multicycle -hold 1 you're saying it can be anywhere between 0ns and 20ns, which I assume is what you want.
(Because of variation between max and min timing models, it is almost impossible to have a path squeeze between 10ns and 20ns, so having just a multicycle -setup 2 without the multicycle -hold 1 is often impossible).Honored ContributorThank you so much for taking the time to reply to my question.
I tried your suggest and added the MC hold constraints. after that the design became unroutable, or cannot fit. if I remove the MC constraints, it can compile and finish; is it possible that the MC constraints are not supplied in compile time but only provided to it at timequest time?Honored ContributorHonored ContributorThank you so much, all is good now.
