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Altera_Forum
Honored Contributor
10 years agoQuartus result not making sense, multicycle resulted in large violations?
my design has wide adders, 42 bit adders. with 10ns clock period, it has -10ns slack. I change the adder path to be multicycle path x2. with data required time being 20ns, the new Quartus compile...
Altera_Forum
Honored Contributor
10 years agoDid you add a multicycle -hold 1 to the same path? Without that, you're telling Quartus the datapath must be greater than 10ns. With the multicycle -hold 1 you're saying it can be anywhere between 0ns and 20ns, which I assume is what you want.
(Because of variation between max and min timing models, it is almost impossible to have a path squeeze between 10ns and 20ns, so having just a multicycle -setup 2 without the multicycle -hold 1 is often impossible).