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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus result not making sense, multicycle resulted in large violations?

my design has wide adders, 42 bit adders. with 10ns clock period, it has -10ns slack. I change the adder path to be multicycle path x2. with data required time being 20ns, the new Quartus compile...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Thank you so much for taking the time to reply to my question.

I tried your suggest and added the MC hold constraints. after that the design became unroutable, or cannot fit. if I remove the MC constraints, it can compile and finish; is it possible that the MC constraints are not supplied in compile time but only provided to it at timequest time?

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MC has nothing to do with routing failure. However I have noticed that if there is sdc syntax error then I get such message. Check all compiler messages.