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sbj's avatar
sbj
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1 month ago

Quartus and power domain

We actually one remaining pending issue with the Agilex chip that we can't get resolved and might need some help.    The basic description is that when comparing the power consumption of the Agilex...
Power
Programmable Logic Device
Farabi_Altera's avatar
Farabi_Altera
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1 month ago

Hello, 

 

Can you response to my inquiry? 

 

regards,

Farabi

sbj's avatar
sbj
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1 month ago

Thank you Farabi for your reponse.

Please allow me some time to provide you a feedback :)

Cheers

  • Farabi_Altera's avatar
    Farabi_Altera
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    1 month ago

    Hello, 

     

    Noted. I will wait for your reply. 

     

    regards,

    Farabi

    • sbj's avatar
      sbj
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      1 month ago

      Hi Farabi,

      here are the answers I received to your questions



      1-can you try power up with slower ramp time? (within timing spec)


      It does not help.

      2- how many boards manufactured? All showing same behavior?

      The behavior is reproducible on all three of our boards. I also observe very similar behavior on the Avnet evaluation board (with a slightly different package). 
      It appears to be temperature-dependent Vcore leakage.

      3- Is it possible to swap unit on the board with another one? 

       to see if the issue follows unit or follows board
      The issue tracks temperature. Internal Agilex temperature sensors show a direct correlation between core rail current and die temperature.

      4- Please send snapshot of the device top marking so I can analyse the production test history. 

      no answer

       

      Cheers

      • Farabi_Altera's avatar
        Farabi_Altera
        Icon for Regular Contributor rankRegular Contributor
        1 month ago

        Hello, 

         

        While waiting the snapshot of topmarking, can you below:

        1- get measurement (resistance value) between VCC to GND (with the FPGA mounted)

        2- All 3 boards showing the same behavior - suspect board design issue. Is it possible to unmount the FPGA and do step 1 above wihout the unit? 

         

        regards,

        Farabi