Qsys project with DDR2 Uniphy won't build anymore..

I have Qsys project that has a Nios II/f, clock input, PLL, UniPhy ddr2, System ID, Jtag Uart, EPCS controller in it. It was building fine in Qsys and then in Quartus as well but I could not program the SOF/ELF into my Boot Flash. I was working on it to resolve this problem when I did "something" that has made the Qsys project not be able to build anymore. I get the following error when Qsys tries to build:

“Error: s0: Error during execution of "{C:/altera/13.0sp1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally”

This is the same error described on Solution ID rd02192013_986 which says to make sure that your TEMP environment variables do not point off your local machine. I made sure that they were not and it did not fix the problem.

I have also done the following and still cannot build it anymore...

1. building the uniphy on Sunday afternoon before 2:00pm so something has happened since then.

2. Qsys project itself seems ok because I can build it on other machines.

3. I uninstalled 13.0sp1 and then reinstalled 13.0sp1 (did not help)

4. I have been successfully building completely new projects with nothing more than the following with no problems:

5. Clock input

6. PLL

7. Sys ID

8. Onchip Ram

9. Jtag uart

10. EPCS controller

11. Nios II

12. As soon as I add the uniphy to the above project it breaks and will not build and shows the error above

13. I completely disconnected from the network and ran off a temp license and it made no difference

14. I copied the following folders from C:\Alera\13.0sp1\ip\altera\* to my project folder and it made no difference

15. ddr2_high_perf

16. emif

17. mem

I'm at a complete loss as to what try next... any good ideas out there from some of you Cyclone V 13.0sp1 UniPhy experts??

I'm thinking all I have left is the registry but I don't really know what to do in that case..

thanks,

david