PWM signal problem

Looks like you have a capacitor in series with your signal. Are you sure you are using the correct oscilloscope probe, in DC mode? What's connected to your pin?

Daixiwen, some sort of input capacitance was my first impression too.

Is the scope set to D.C. coupling?

batfink, he result is identical in either AC or DC couplings.

  -- every 3.84 uS - short pulse generates clock Tick 
  process (Clk)
  begin
  if (rising_edge(Clk)) then
       ClkCount <= ClkCount+1;
       if (ClkCount = 96) then     
     ClkTick <='1';
     ClkCount <= (others =>'0');
    else
     ClkTick <='0';
       end if;
   end if;
  end process;
 
  -- resets PulseCounter at 30 ms 
  -- PulseCounter is 13 bits long shared variable
  process (Clk,ClkTick)
  begin
   if (rising_edge(Clk)) then
    if(ClkTick ='1') then 
       PulseCounter := PulseCounter+1;
       if (PulseCounter = PulsePeriodRes) then
    PulseCounter := (others =>'0');
  end if;
  end if;
  end if;
  end process;
 
 -- Rxd_data is the compare value 
  process (Clk)
  begin
   if (rising_edge(Clk)) then
    if(PulseCounter<  Rxd_data) then
     Pwm_out<='1';
    else
     Pwm_out<='0';
    end if; 
   end if;
  end process;

I don't think tit comes from the VHDL code, it's most likely a hardware problem.

By the way why are you using a shared variable? It isn't recommended because of its non-deterministic behaviour. You have no way of forcing the execution order of your two processes. You should either merge the two processes, or use a signal.

I agree with Daixiwen - check the solder joints or try another pin.

Daixiwen, definitely is not VHDL code. I tried different pins like 41, 144 but the same result. Is good to know that variables causes non-deterministic behaviour - elegant explanation.

Unfortunately the oscilloscope screenshot has no scaling information, otherwise one could restrict the number of possible explainations. A time expanded view would be also meaningful. But anyway, a FPGA I/O hardly can't source a similar waveform. An oscilloscope probe inadvertently connected to a 50 ohms input may expose it (depending on the selected timebase), also a defective probe. But it's basic electronics, not particularly related to FPGA.

FvM , here is a screen with timing information - 1ms per division.