batfink, he result is identical in either AC or DC couplings.
I also created short VHDL code that behaves similar to above.
-- every 3.84 uS - short pulse generates clock Tick
process (Clk)
begin
if (rising_edge(Clk)) then
ClkCount <= ClkCount+1;
if (ClkCount = 96) then
ClkTick <='1';
ClkCount <= (others =>'0');
else
ClkTick <='0';
end if;
end if;
end process;
-- resets PulseCounter at 30 ms
-- PulseCounter is 13 bits long shared variable
process (Clk,ClkTick)
begin
if (rising_edge(Clk)) then
if(ClkTick ='1') then
PulseCounter := PulseCounter+1;
if (PulseCounter = PulsePeriodRes) then
PulseCounter := (others =>'0');
end if;
end if;
end if;
end process;
-- Rxd_data is the compare value
process (Clk)
begin
if (rising_edge(Clk)) then
if(PulseCounter< Rxd_data) then
Pwm_out<='1';
else
Pwm_out<='0';
end if;
end if;
end process;