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Honored Contributor
Honored ContributorPWM signal problem
Hello, could someone explain a strange problem with PW signal. The signal period is 30 ms, and PW triggers in between 0.7 and 2,2 ms. But, I'v got a problem since the moment the signal...
Altera_ForumHonored Contributor
Honored ContributorUnfortunately the oscilloscope screenshot has no scaling information, otherwise one could restrict the number of possible explainations. A time expanded view would be also meaningful. But anyway, a FPGA I/O hardly can't source a similar waveform. An oscilloscope probe inadvertently connected to a 50 ohms input may expose it (depending on the selected timebase), also a defective probe. But it's basic electronics, not particularly related to FPGA.
Regarding your last question, the synthesis tool is trying to achieve a specified design speed, but not slowing down the design. Why should it?
