Forum Discussion
Honored ContributorPWM signal problem
Hello,
could someone explain a strange problem with PW signal. The signal period is 30 ms, and PW triggers in between 0.7 and 2,2 ms. But, I'v got a problem since the moment the signal rise it falls down again just like in the following picture. http://img396.imageshack.us/img396/7549/pulse.png I wonder if I have to assign special characteristics to the output pin in Quartus pin assignment sheet. I think VHDL code is ok. Perhaps some silly thing I overlooked.18 Replies
Altera_ForumWell done - these things are sent to try us
- Altera_Forum
I rather think, a missing piece of wire ...
- Altera_Forum
Daixiwen, batfink, FvM , thank you very much.
I found the problem. It was a short patch of wire between the board pin and probe. I totally neglected its significiance , very silly me who did not think it can cause such an attenuation. Now when I checked the pin directly, the signal is perfect with no noise and with perfect shape. - Altera_Forum
It seems to be basically the same issue of a capacitive coupled signal. Because of higher frequency, you see (almost) a square wave now. The problem is neither related to VHDL, sensitivity lists nor FPGAs in particular.
P.S.: You may want to start by assigning a static DC level ('H' or 'L') to some output pins and trace it with a multimeter. FPGAs have, by the way, a trivial method of disabling all outputs by enabling the global DEV_OE pin in device options without asserting it. You should exclude this option, too. Also supplying no VCCIO to a bank may possibly have similar results. - Altera_Forum
FvM, I think the board is faulty. But one more thing before I finalize my conclusion: what about this signal produced by VHDL single counter and no signals in sensitivity list. The peak to peak is just 10 - 12 mV. Have I done something wrong or do I miss something ?
http://img128.imageshack.us/img128/2865/pulse3.png - Altera_Forum
If the probe is known to work correct, you may be probing a wrong pin. check the neighbours too.
- Altera_Forum
FvM, the noise level is around 1.4 mV and
http://img230.imageshack.us/img230/7915/noise.png Vpp level is shown as 28 mV ? I have no clue why doesn't go to 3.3 V. http://img201.imageshack.us/img201/5296/voltage.png What do you mean that the signal may come --- Quote Start --- instead from an unconnected trace running directly beneath the driven signal. --- Quote End --- I probed the output pin, not traces on the board. - Altera_Forum
So the high pass time constant is in a 100 us Range. When I asked for the waveform scaling, I also referred to the voltage (level of wide noisy line and peak-to-peak value.)
If I understand the trigger level display correct, the base line is around zero and the negative peak is actually below zero. A level, that can never be driven actively by a FPGA I/O that's really connected to this signal. You could pick it up instead from an unconnected trace running directly beneath the driven signal. - Altera_Forum
FvM , here is a screen with timing information - 1ms per division.
http://img48.imageshack.us/img48/2120/pulse2.png I have checked the osciloscope probe against a low frequency signal generator and it works fine. I "assume" the attenuation is likely capacitive load sort of high pass filter, but no idea what it could be, because nothing stands in between the pin and probe. Generated 3 khz signal on pin is relativly OK, slightly different code without the prescaler counter. I also tried to drive a small RC servo and such signal just holds it on spot. model. But slightly smaller size RC servo responds and moves corresponding to the signal. - Altera_Forum
Unfortunately the oscilloscope screenshot has no scaling information, otherwise one could restrict the number of possible explainations. A time expanded view would be also meaningful. But anyway, a FPGA I/O hardly can't source a similar waveform. An oscilloscope probe inadvertently connected to a 50 ohms input may expose it (depending on the selected timebase), also a defective probe. But it's basic electronics, not particularly related to FPGA.
Regarding your last question, the synthesis tool is trying to achieve a specified design speed, but not slowing down the design. Why should it?
