PWM signal problem

It seems to be basically the same issue of a capacitive coupled signal. Because of higher frequency, you see (almost) a square wave now. The problem is neither related to VHDL, sensitivity lists nor FPGAs in particular.

P.S.: You may want to start by assigning a static DC level ('H' or 'L') to some output pins and trace it with a multimeter. FPGAs have, by the way, a trivial method of disabling all outputs by enabling the global DEV_OE pin in device options without asserting it. You should exclude this option, too. Also supplying no VCCIO to a bank may possibly have similar results.