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Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

programming successful but no function of CPLD

Hi, I am quite new with CPLD design and hope to get help here.

For test purposes and learning I made a simple schematic with an external clock of 1 kHz, a 4bit counter (74161) and a BCD to 7 segment decoder (7448). All 4 outputs from counter and 7 outputs from decoder are available on pins of the CPLD.

I programmed a MAX300 EPM3064ATC44 on a self made board with a USB Blaster Rev. c. Quartus II programmer reported 100% successful programming and verification. But the counter outputs don't look like binary counting. They are totally confused.

I also programmed the same schematic to a MAXII EPM240T100 on a test board from ebay. Again programming was successful but counter outputs are confused.

The USB Blaster is a clone from ebay. It contains a STM32FEB but no output driver for level conversion. Both boards, my self made one and the board from ebay, are powered with 3.3 V and also VCC_IO for both chips is 3.3 V. Therefore level conversion is not necessary.

The board from ebay was delivered programmed with a blinking example. Therefore the chip should be ok.

What could have happened that after successful programming the chips don't work as expected?

A picture of the ebay board and USB Blaster ist attached.

  • Hi,
    which series resistor value? Clock edge may be too slow and cause multiple transitions. As you say it's a self designed board, insufficient power supply bypassing and ground bounce can cause irregular CPLD behaviour.

8 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor

    Hi,
    I suspect your code in the first place.

    • Niko3's avatar
      Niko3
      Icon for Occasional Contributor rankOccasional Contributor

      I didn't write code. I used the block editor to design the schematic, see attachment (for EPM240).

      I also made a simulation which showed correct waveforms.

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        Hi,
        how do you observe the counter output? What's the 1 kHz external clock source, sure it's suited as CPLD clock?
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