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Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

programming successful but no function of CPLD

Hi, I am quite new with CPLD design and hope to get help here. For test purposes and learning I made a simple schematic with an external clock of 1 kHz, a 4bit counter (74161) and a BCD to 7 segment...
Board Debug
Configuration
Programmable Logic Device
  • FvM's avatar
    FvM
    3 years ago

    Hi,
    which series resistor value? Clock edge may be too slow and cause multiple transitions. As you say it's a self designed board, insufficient power supply bypassing and ground bounce can cause irregular CPLD behaviour.

NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
2 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.