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Altera_Forum's avatar
Altera_Forum
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16 years ago

problem with cyclone III and jtag

I would like to put a very serious discussion about using jtag with cyclone III.

has cyclone3 less electrical tolerance compared to other FPGA's??????

. we are building a custom board. and to my horror 2 of them have suddenly stopped to down load .sof. Till yesterday every thing was fine, but when i started to work today i find them unable to detect jtag chain.

My jtag cable is from terasic. I have used the same schematic as given in altera configuration handbook for cyclone3. I am configuring the FPGA in AS well as in jtag mode. I'm able to download .pof.

After reading so many posts regarding jtag and cyclone3, I am in confusion wether the FPGA has gone bad or the jtag.

Is there any special protection that needs to be taken when using cyclone3 with Jtag.

Kindly help its very urgent. Can anyone plz provide a schematic for interfacing jtag with cyclone3.

regards

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    What voltage are you using for the JTAG interface? There is an issue when you use 3.0 or 3.3V for the Jtag signals, if you don't add external clamping diodes. If an overshoot voltage goes over 4.1V it can destroy the I/O buffer of the FPGA.

    Usually if I have the space I put a buffer on the PCB between the FPGA and the JTAG connector, for protection.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Sorry for the late response. I was busy in debugging the issue, but of no success. we are using 3.3v . but we have not used any clamping diode coz there is no such mention in the schematic diagram given in altera configuration handbook.

    Plz let us know is putting the clamping diode neccessary. ??? What other things do i need to check. I am using epc3120fc8n.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Page 9-49 of the Cyclone III datasheet:

    http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf

    reads:

    --- Quote Start ---

    For device VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–24. All I/O inputs must

    maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal

    PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and

    3.3 V, you must power up the VCC of the download cable with a 2.5-V supply from

    VCCA.

    --- Quote End ---

    It is unfortunate that this was overlooked. You say the boards had been working and have failed. It is possible that the FPGA has been damaged.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    A 3.3V USB Blaster supply doesn't necessarily imply overshoot and vioaltion of the maximum ratings. It depends on the board design, particularly trace impedance and length. But clamping diodes are a good idea in any case.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the response. we have send the boards for adding clamping diode.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I have one more question.

    I u look in the cyclone3_handbook figure 9-7. It shows to put the clamping diode for the AS mode. though it talks of the same in the jtag mode, but it never shows in any diagram.

    KIndly correct if I am wrong.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You are right. They don't put the clamping diodes on figure 9-24, and instead recommend to use vcca (2.5V) as the jtag i/o power supply instead of the bank 3.0/3.3V supply. It works too, but I find the clamping diodes safer.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    If the supply is given 3.3V instead of VCCA i.e 2.5, is it damages the FPGA. In our board we are using 3.3V instead of 2.5V. The board is working in JTAG configuration. But after some time in two to three boards We are facing the JTAG port defective in our board as ashishsingh says. Please confirm. And also suggest any buffer that can be put in between JTAG port and FPGA

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It shouldn't damage the FPGA, as long as the voltage never goes above 4.1V. The I/O voltage used for the JTAG pins is the same than for bank 1, and extra care should be taken if you are using a supply voltage of 3.0 or 3.3v.

    Any high speed buffer should do the trick. We use 74LVC541 chips and they work fine.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    You are right. They don't put the clamping diodes on figure 9-24, and instead recommend to use vcca (2.5V) as the jtag i/o power supply instead of the bank 3.0/3.3V supply. It works too, but I find the clamping diodes safer.

    --- Quote End ---

    Is it a problem to use VCCA 2.5V AND put something like the SN74LVC541 buffer in between the FPGA and JTAG connection? Do you advise that TCK, TMS, TDI, and TDO all go through the buffer.