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Honored Contributor
15 years agoI am implementing a connection as shown in the following reference which shows programming a serial device through JTAG:
Figure 9-30 on page 60 of cyc3_ciii51016-2.pdf We are using the USB-Blaster cable. I've inserted the 74LVC541 between the connector and the FPGA for the 4 JTAG signals. Pin6 of the JTAG 10 pin connector is a No Connect and Pin 4 is connected to VCCA 2.5V. The pull ups for TDI and TMS are to VCCA 2.5V. Our cycloneIII is configured such that B1 is 3.3V which contains the JTAG signals. The nCONFIG and nSTATUS signals are pulled up as they are in the above reference to VCCIO1(3.3V). The CONF_DONE signal is in B6 and is pulled up to VCCIO6 of 1.5V. All other connections are exactly as shown in the reference above. Does this capture all your recommendations on how to ensure the FPGA is protected? Did I miss something?