Forum Discussion
Altera_Forum
Honored Contributor
15 years agoIt shouldn't damage the FPGA, as long as the voltage never goes above 4.1V. The I/O voltage used for the JTAG pins is the same than for bank 1, and extra care should be taken if you are using a supply voltage of 3.0 or 3.3v.
Any high speed buffer should do the trick. We use 74LVC541 chips and they work fine.