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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problem while loading a program with a time limited sof

Hello everyone,

I'm a french student from Polytech'Paris and I'm currently working on a project which has to use PCIe input and Ethernet output of the Stratix IV GX development board. I have to receive market data coming from the PCIe and send out some analytics as fast as possible with the Ethernet output.

I already managed to receive data and read them from the PCIe and my .sof .elf work perfectly on my computer running on linux.

For the output, I only use an Ethernet Generator, an Ethernet Monitor and a Triple Speed Ethernet provided by Altera.

Now that I have my time_limited_sof I load it on my board and try to run a Hello World but everytime I do I get the problem that is described here:

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Using cable "USB-Blaster [USB-0]", device 1, instance 0x00. Pausing target processor: not responding. Resetting and trying again: FAILED. Leaving target processor paused

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From what I've seen on this forum:

-I'm not closing the windows which says that I'm working with a time_limited sof (I also tried to load my time_limited_sof using nios2-configure-sof ...time_limited.sof)

-My clock is working fine (it's the same design as the one I used before)

-My unused pin are in tri-stated with weak pull-up

-My reset button is already connected to a toggle switch and I tried to upload my program with my switch in the position 0 and 1.

I'm working on a computer with RedHat Linux 5.5, Quartus 11.0 Full version (licensed) and NiosII IDE.

In order to load the .elf file, I use NiosII IDE (and I also tried to use nios2-download -g ...elf)

Has anyone ever resolved this problem before?

Thank you by advance.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Did you specify timing constraints on your design and does it meet all timing requirements?

    If you use plls, are they properly locked?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thank you, I just found out that my design doesn't meet all timing requirements.

    My PLL are properly locked.

    I'm changing my timing requirement right now