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Altera_Forum
Honored Contributor
15 years agoProblem while loading a program with a time limited sof
Hello everyone, I'm a french student from Polytech'Paris and I'm currently working on a project which has to use PCIe input and Ethernet output of the Stratix IV GX development board. I have to...
Altera_Forum
Honored Contributor
15 years agoDid you specify timing constraints on your design and does it meet all timing requirements?
If you use plls, are they properly locked?