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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem while loading a program with a time limited sof

Hello everyone, I'm a french student from Polytech'Paris and I'm currently working on a project which has to use PCIe input and Ethernet output of the Stratix IV GX development board. I have to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you, I just found out that my design doesn't meet all timing requirements.

My PLL are properly locked.

I'm changing my timing requirement right now