I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and creates the VHDL and symbol without issue. When I try to use the symbol in a project, I am unable to compile the project and get the following error. Error (10481): VHDL Use Clause error at lpm_dff_0.vhd(28): design library "work" does not contain primary unit "lpm_components" Error (10800): VHDL error at lpm_dff_0.vhd(28): selected name in use clause is not an expanded name Can help with why this rather straight forward application using only basic Quartus components would give this error? Are there some settings in generating the VHDL that are not correct? I have not changed anything and tried reinstalling. Any help would be greatly appreciated.

You need to import the respective Altera libraries. Review the MegaWizard generated code about the correct naming.

Do you mean the standard Quartus setup requires the import of Altera files in order to work? Can you give me some more detail about how this is accomplished?

--- Quote Start --- Do you mean the standard Quartus setup requires the import of Altera files in order to work? Can you give me some more detail about how this is accomplished? --- Quote End --- Its not Quartus, its a requirement of the VHDL language ... -- Altera LPM components library lpm; use lpm.lpm_components.all; Cheers, Dave

I was hoping someone had seen a similar problem so I wouldn't have to get into too great a detail, but here goes. When I received the original error, I found the following lines in the VHDL generated by the Altera Megafunction for LPM_DFF-- -- use the following when compiling in Quartus II --LIBRARY lpm; --USE lpm.lpm_components.all; -- use the following when compiling in third party tools -- -- add lpm_pack.vhd from the Quartus II library LIBRARY work; USE work.lpm_components.all; I commented out the work one and uncommented the LPM one as follows-- -- use the following when compiling in Quartus II LIBRARY lpm; USE lpm.lpm_components.all; -- use the following when compiling in third party tools -- -- add lpm_pack.vhd from the Quartus II library --LIBRARY work; --USE work.lpm_components.all; This led me to this error--- Error (10482): VHDL error at lpm_dff_0.vhd(44): object "lpm_dff" is used but not declared When I commented out the _0 lines and changed them to take off the _0 as in the following VHDL--- -- PROGRAM "Quartus II 32-bit" -- VERSION "Version 12.1 Build 177 11/07/2012 SJ Web Edition" -- CREATED "Thu Jan 17 23:22:14 2013" LIBRARY ieee; USE ieee.std_logic_1164.all; -- use the following when compiling in Quartus II LIBRARY lpm; USE lpm.lpm_components.all; -- use the following when compiling in third party tools -- -- add lpm_pack.vhd from the Quartus II library --LIBRARY work; --USE work.lpm_components.all; --ENTITY lpm_dff_0 IS ENTITY lpm_dff IS PORT ( clock : IN STD_LOGIC; data : IN STD_LOGIC_VECTOR(0 TO 0); q : OUT STD_LOGIC_VECTOR(0 TO 0) ); --END lpm_dff_0; END lpm_dff; --ARCHITECTURE bdf_type OF lpm_dff_0 IS ARCHITECTURE bdf_type OF lpm_dff IS BEGIN -- instantiate LPM macrofunction b2v_inst : lpm_dff GENERIC MAP(LPM_WIDTH => 1) PORT MAP(clock => clock, data => data, q => q); END bdf_type; I got the following error-- Error (10349): VHDL Association List error at lpm_dff_0.vhd(48): formal "LPM_WIDTH" does not exist Since this indicates the key paramter LPM_WIDTH is not there in substantiated VHDL, I sent out this cry for help. What doesn't make sense to me is why Quartus would generate VHDL that is not usuable in Quartus!! Does anyone have any ideas keeping in mind that I am not generating the VHDL in question but it is being generated by Quartus.

Are you sure you have copied the code correctly? According to: http://www.altera.com/support/examples/vhdl/v_testdff.html The LPM component is LPM_FF, not LPM_DFF. A search in my 11.1sp1 installation shows the LPM component (C:\software\altera\11.1sp1\quartus\eda\sim_lib\ 220pack.vhd): component LPM_FF generic(LPM_WIDTH : natural; -- MUST be greater than 0 LPM_AVALUE : string := "UNUSED"; LPM_SVALUE : string := "UNUSED"; LPM_PVALUE : string := "UNUSED"; LPM_FFTYPE: string := "DFF"; LPM_TYPE: string := L_FF; LPM_HINT : string := "UNUSED"); port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '1'); CLOCK : in std_logic; ENABLE : in std_logic := '1'; SLOAD : in std_logic := '0'; SCLR : in std_logic := '0'; SSET : in std_logic := '0'; ALOAD : in std_logic := '0'; ACLR : in std_logic := '0'; ASET : in std_logic := '0'; Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); end component; The comments in the example code regarding third party tools are incorrect. All tools can use the LPM library. You just need to create the LPM library, or map it to the work library. For example, in Modelsim vlib lpm vmap lpm [pwd]/lpm or vlib work vmap lpm [pwd]/work and then compile the components into that library vcom -work lpm 220pack.vhd vcom -work lpm 220model.vhd Modelsim-ASE already has this library configured with the source built into it. Cheers, Dave

Problem using VHDL from a project lower in the heirarchy in an upper level

14 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I am just manually setting the inputs and output in modelsim to do the simulation testing.
--- Quote End ---

Manually? How, using force statements, or using a top-level VHDL testbench.

Its hard to help you if I have to guess. Just post your code, or some minimal code that demonstrates the error.

The testbench that I referred you to probably has enough to get you started - try running it.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I have traced my problem to connectivity problems where it say some of the Q output of my FF's are connected dangling logic. I have try renaming, renumbering, splitting, and finally connect my buses only by signal names. I have attached my BDF file is someone can look at it and see what my problem is, I would be eternally grateful.
PLD_Proxy.zip27 KB
Altera_Forum
Honored Contributor
13 years ago
Dave I didn't see your previous reply before sending out my previous one. First, let me say thanks for your patience. I spent 3 years working with Quartus on multiple projects, but the last one was 5 years ago. Things have certainly changed a bit. To answer you question, only needed the equivalent of three clocks to test this circuit, so I just manually applied then using the same facility as force. Sorry if I was not clear enough in the past.
Altera_Forum
Honored Contributor
13 years ago
I opened up PLD_Proxy, and although you have a top-level BSF, and what looks like a generated top-level VHDL file, I do not see a testbench file, eg., PLD_Proxy_tb.vhd.

Without that file, you're not going to get very far with simulation. I'd recommend taking the time now to create a basic testbench containing a clock generator, and a process that drives valid signals onto the input ports. At that point you will be able to see whether the output ports are all driven to valid values. Then you can start to add test sequences. The testbench I posted should be enough to get you started.

Cheers,
Dave

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Problem using VHDL from a project lower in the heirarchy in an upper level

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