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Altera_Forum's avatar
Altera_Forum
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18 years ago

Problem uploading design to Cylone II

Hi,

i have the nios development board (cyclone II edition), which has an altera cyclone II EP2C35F672C6 FPGA.

The problem i'm facing is that everytime i use the quartus 2 programmer to upload a design looks like the board reboots and loads the factory config (that one with the web server running in a nios II processor).

I really don't know what i'm doing wrong... Any ideas? (Is there a locking mechanism or something like that?)

Cheers, Milosevic.

PS: ALthough the programmer always says "configuration successed", the "User" led never blinked... the "factory config" led is always on..

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello,

    I guess, you are using the EPCS configuration. It should be loaded first and only skipped if invalid. You can verify the programmed EPCS image with the programmer, to check if it's identical to *.pof file. It could also be invalid, if it's dedicated to another device than the EP2C35. To check your configuration, you can load it non-permanently via "JTAG->U62", JTAG configuration overrides PS configuration from configuration controller.

    If the EPCS image doesn't verify correct, it may be an USB Blaster issue. Cyclone II Nios evaluation Board (at least my exemplar) has been shipped with USB Blaster Rev. 1, the JTAG interface was changed with newer USB Blaster Revisions. If I remember right, I changed the TCK/DCLK (Pin 1) series resistor to 100 ohms, it had been 10 ohms or less originally. Also the original flexprint cable could easily be damaged and should be replaced by a short standard IDC cable to my opinion. JTAG programming, to my experience is also possible with a longer cable, but with AS programming, the cable length is critical.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I've seen similar behaviour when the setting "Reserved all unused pins" are set to output driving ground. I think it has something to do with the FPGA grounding a active low signal to the configuration CPLD, which activates reprogramming of factory settings. If you haven't already done this set unused pins to "input tri-stated".

    //Ola
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I was experiencing the same problem. I tried changing the unused pins setting under device settings to "inputs tri-stated" and it worked! Thanks!