Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Problem uploading design to Cylone II

Hi, i have the nios development board (cyclone II edition), which has an altera cyclone II EP2C35F672C6 FPGA. The problem i'm facing is that everytime i use the quartus 2 programmer to upl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

I guess, you are using the EPCS configuration. It should be loaded first and only skipped if invalid. You can verify the programmed EPCS image with the programmer, to check if it's identical to *.pof file. It could also be invalid, if it's dedicated to another device than the EP2C35. To check your configuration, you can load it non-permanently via "JTAG->U62", JTAG configuration overrides PS configuration from configuration controller.

If the EPCS image doesn't verify correct, it may be an USB Blaster issue. Cyclone II Nios evaluation Board (at least my exemplar) has been shipped with USB Blaster Rev. 1, the JTAG interface was changed with newer USB Blaster Revisions. If I remember right, I changed the TCK/DCLK (Pin 1) series resistor to 100 ohms, it had been 10 ohms or less originally. Also the original flexprint cable could easily be damaged and should be replaced by a short standard IDC cable to my opinion. JTAG programming, to my experience is also possible with a longer cable, but with AS programming, the cable length is critical.

Regards,

Frank