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Altera_Forum
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18 years ago

Problem uploading design to Cylone II

Hi, i have the nios development board (cyclone II edition), which has an altera cyclone II EP2C35F672C6 FPGA. The problem i'm facing is that everytime i use the quartus 2 programmer to upl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I've seen similar behaviour when the setting "Reserved all unused pins" are set to output driving ground. I think it has something to do with the FPGA grounding a active low signal to the configuration CPLD, which activates reprogramming of factory settings. If you haven't already done this set unused pins to "input tri-stated".

//Ola