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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem in running NIOS II Software Project on Altera

I keep getting this error while trying to run software projects built in NIOS II IDE

using cable "usb-blaster [usb-0]", device 1, instance 0x00

pausing target processor: not responding.

resetting and trying again: failed

leaving target processor paused

I've re-synthesized the standard niosII_cycloneII_2c35 example and did the pin assignments correctly.

(but while building the programmable file it says time limited version )

Is it a licensing issue ?

Can someone plz help me ?

Thanks in advance.

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    When you configure the FPGA with a time limited .sof, you have a window that opens, telling you that you are in opencore evaluation mode. Don't close this window, or the CPU will stop working.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    After the device is programmed with time limited .sof file it showed a dialog box such as

    OpenCore Plus Status

    Click Cancel to stop using OpenCore Plus IP.

    Time Reamaining unlimited

    Cancel

    i never closed this window but i still get the same error

    Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

    Pausing target processor: not responding.

    Resetting and trying again: FAILED

    Leaving target processor paused

    Could there be anymore reason why it is not responding.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    when u load your .sof (in Quartus II prgrammer) for your particular system or board,Is this

    for that board or other pls check it.

    Or some time you not configure FPGA with .sof and run your project it might show above error.

    Regards,

    jayesh
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hey jayesh thanks for the support

    I re-chose the device family , synthesized and then loaded into the board.

    I think i made a little development from the previous error. But still it shows new errors

    Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

    Pausing target processor: OK

    Reading System ID at address 0x021208B8: verified

    Initializing CPU cache (if present)

    OK

    Downloading 02100020 ( 0%)

    Downloading 04000000 ( 0%)

    Downloading 04010000 (88%)

    Downloaded 73KB in 1.2s (60.8KB/s)

    Verifying 02100020 ( 0%)

    Verifying 04000000 ( 0%)

    Verify failed between address 0x4000000 and 0x400FFFF

    Leaving target processor paused

    What else can i do ?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    @sudattuladhar

    I am pretty sure that this type of error occurs because of u load wrong .sof on your board,

    if possible pls contact who design(IP devloper) .sof for your system and varify from them.

    and if possible design new .sof for your system and again try it.

    Regards,

    jayesh
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi sudattuladhar,

    A few question that can help to understand where the problem is:

    - Are you sure your fpga design meets timing requirements?

    - What's the Nios clock frequency you are using?

    - Are you loading the program into onchip ram or in a sdram?

    - if your code is loaded in sdram,, are you sure it is working correctly and timing is correct?

    Regards
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Most frequent cause of this is that your design is not meeting timing requirements or you have not properly constrained the timing.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What kind of memory do you have at address 04000000? If this is external memory and you also have on-chip memory, you could run a memory test.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Finally Success with Hello-World NIOS II Software Project with LEDs and Switches

    Had to make these changes.

    1. Created a new .sof file all over from scratch

    2. Instantiated the new processor in schematic file and connected the input and output ports

    3. Made proper pin assignments for input and output ports

    - Didn't have to consider timing requirements

    - Had to map the reset button to a toggle switch and kept in in high logic

    tut_sopc_introduction_vhdl.pdf had been a great help .

    Thank you All for supporting !!!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    That's great.............

    We not realy help you.

    but anyway You are Welcome

    Regards,

    Jayesh