Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi sudattuladhar,
A few question that can help to understand where the problem is: - Are you sure your fpga design meets timing requirements? - What's the Nios clock frequency you are using? - Are you loading the program into onchip ram or in a sdram? - if your code is loaded in sdram,, are you sure it is working correctly and timing is correct? Regards