Problem in Implementing Autocorrelation on Stratix II EP2S60 DSP Development Board

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I am having a hard time with my ADC. Its AC coupled and changes the signal I send. Could you please send me something about handling the ADC.

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If the ADC is AC coupled, then it will have a low-frequency limit. You need to check the bandwidth of the AC coupling circuit. Is it just some capacitors or is it a balun? Are you using an Altera board, or custom board?

There are some spectra in here from the Stratix II DSP Kit:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

The spectrum looks fine at 3MHz (if this is the board you are using).

Cheers,

Dave

I am having a hard time with my ADC. Its AC coupled and changes the signal I send. Could you please send me something about handling the ADC.

Thanks bro,

Saket

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I am working with frequencies of 3MHz(transmitted signal) and trying to make a model of visible light communication.

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That's a little vague.

What are you trying to do "in detail".

You have a DSP board, what are you sending to the DAC, what are you sending to the ADC? Do you have two boards that are supposed to communicate, or are you just looping things back on the same board? How are the TX and RX connected, eg. just a wire, or are you using the 'visible light communications' interface? What is that interface, and IR source? Are the source and destination using the same clock, or are they asynchronous?

What kind of direction have you been given for this project?

Cheers,

Dave

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hope you are fine on the other end. I am not so fine as the transmitter and receiver are not getting synchronized :(

I am trying to use the peak of auto-correlation to synchronize but I think its not the best way.Could you please suggest any other technique to synchronize? I just need to find the delay of channel so that I can guide receiver to decode data.

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Please describe your hardware setup in a little more detail.

What are you actually trying to do?

What are the frequencies of operation?

Cheers,

Dave

Hey Dave,

hope you are fine on the other end. I am not so fine as the transmitter and receiver are not getting synchronized :(

I am trying to use the peak of auto-correlation to synchronize but I think its not the best way.Could you please suggest any other technique to synchronize? I just need to find the delay of channel so that I can guide receiver to decode data.

Please help!!!!

Saket

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I was trying to program it on the board and it wouldn program. I was asking if any extra care I need to take for implementing the megacore on the board.

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If you do not have an FIR Compiler license, then I believe you need to keep the JTAG cable connected. Even then, the design might become non-functional after some time. You will need to read the messages from Quartus, I believe they will tell you what the limits on the design are.

These limits will not occur in the simulator.

Cheers,

Dave

hey Dave,

thanks for the suggestions but I have only configured my fir_compiler megacore and its working fine in dsp builder. I was trying to program it on the board and it wouldn program. I was asking if any extra care I need to take for implementing the megacore on the board.

Cheers,

Saket

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I have almost completed my design. Now I have the problem implementing it on the board. I guess the problem is because of FIR Megacore I am using. Could you please help me with implementing FIR Megacore on the board?

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No, not without an explanation of what you decided to design :)

Please explain your system-level design, and then people can help.

Before you work with the Altera tools, you need to design the filter(s).

For example, if you know the frequency of the signal you are trying to detect the power of, then your design could be implemented per the discussion in this thread;

http://www.alteraforum.com/forum/showthread.php?t=30284&page=3

I just posted a MATLAB script showing how to decimate a high-rate sampled signal, to a low-rate sampled signal. The script shows that the particular combination of filters meets the design requirements, however, the script is not an HDL implementation. The next task for the person I was responding to, is to go and implement these filters in CIC Compiler, and FIR Compiler II.

In your design, you would demodulate your received signal using the known frequency (generated using an NCO with quadrature outputs), low-pass filter and decimate (both the in-phase and quadrature components), and then calculate the power.

Cheers,

Dave

hey...thanks for all your help. I have almost completed my design. Now I have the problem implementing it on the board. I guess the problem is because of FIR Megacore I am using. Could you please help me with implementing FIR Megacore on the board?

Thanks

saket