problem about por

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but my reset chip max708s has only 200ms of power on reset.then after the fpga finish config,it cannot going to reset state , How can I resovle this problem

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Sounds like unsuitable reset logic. External asynchronous resets needs to be synchronized to achieve an synchronous release. This logic logic should also work, if the external reset has ended before configuration.

The MAX708 still works as a power supply supervisory, but you probably may want to use a chip with longer delay.

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I am confused by the power on reset recently. When I power on my board,the fpga must load configration from epcs16,it use much time,but my reset chip max708s has only 200ms of power on reset.then after the fpga finish config,it cannot going to reset state , How can I resovle this problem

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Use a reset chip that supports external reset source, eg. a push button.

Drive the push-button input to the reset chip from a group of active-low drivers; one being a reset push-button, the other derived from the FPGA configuration done (CONF_DONE) pin. When CONF_DONE goes high, its analogous to a push-button being released.

For an example of this, see page 95:

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)

CONF_DONE drives the output-enable on a tri-state buffer, which then drives a reset chip. Note 2 indicates the reset controller ICs that can be used.

Now the sequence will be;

1) FPGA is not configured, CONF_DONE is low, reset is active.

2) FPGA configures, CONF_DONE is high, reset deasserts

3) Internal FPGA reset synchonizers release reset synchronous to their respective clock domains, and user logic is enabled.

Cheers,

Dave