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Altera_Forum's avatar
Altera_Forum
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14 years ago

problem about por

I am confused by the power on reset recently. When I power on my board,the fpga must load configration from epcs16,it use much time,but my reset chip max708s has only 200ms of power on reset.then aft...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If your design has an internal PLL that is sourced from a free-running clock you can use the PLL lock indication as an active low reset.