Possible causes of dead cyclone IV on custom board

Question

Hello,

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes:

I am using 3.3V VCCIO for all IO banks. I misread the handbook and connected TMS and TDI pins on the 3.3V VCC instead of 2.5V VCCA. After realising this, i corrected it but it might be too late. Would this be enaugh, to fry the JTAG?
After soldering the chip in place, i failed to notice in time there are about two to five solder bridges between pins. Some of them shorted my 3.3V VCC. After i realized this, i reworked the chip and triple checked for any bridges. There are not any.
Because of the problems mentioned above, i had to solder and desolder the chip twice. I was using hot air station. I tried to controll the temperature as well as i could (with thermocoupple right on top of the chip) but i did it by hand. Could it be damaged by the heat?

When i connect the board to the USB blaster, quartus says that it could not initiate JTAG chain, because no devices were found. I tried debugging the jtag using oscilloscope, but since this is my first time trying to do it, i do not know what exactly to look for. I noticed the following:

When using JTAG debugger and setting how many clock pusles to send, clock signal looked quite weird. If i sent less than 8 pulses, the scope showed quite nice square wave. But when setting the clock to send more pulses, the signal became weird. There were few nice pulses as before and then there were random bursts of pulses of about 6x the frequency of the original ones. At first i thought they were just noise, but they were perfectly uniform. Almost seemed like the programmer would try to communicate on different frequencies. I do know if this is normal behavior of JTAG or not.
The TDO pin was staying high all the time. Which i assume is a sign of broken jtag interface in fpga.
Other pins were showing some data, but i do not know enough about the protocol to say, if it was correct.

Every VCCIO is connected to the 3.3V, every VCCA to 2.5V and every VCORE is connected to the 1.2V. Coud the problem be, that VCCIO of the bank where JTAG resides is 3.3v?

I am sorry if i forgot something or sound too stupid. This is my first fpga project so please be kind. :-)

Thank you in advance for all your replies!

altera_forum · Answer

Well done for persisting, top marks for effort...

In answer to your questions:

1) I assume by this you mean you connected the pull-ups on TDI & TMS to 3.3V? That, on it's own, is not enough to fry your JTAG circuitry.

2) Solder bridges could cause a problem. However, frequently they simply prevent the FPGA working properly - until you remove the bridge, or they cause your power supply a problem due to excessive load.

3) Yes, you could damage it with heat - although they are pretty tolerant. I suspect the lack of accuracy in the temperature control you describe won't help.

If looking at the JTAG signals with an oscilloscope, as you mention, you're looking for something on TDO. It's perfectly acceptable for TCK to vary in frequency and (perhaps) try different ones. Do you seen any activity on TDI or TMS?

It's perfectly valid to power all the I/O at 3.3V, providing VCCA is 2.5V.

Have a look at post 49934 (http://www.alteraforum.com/forum/showthread.php?t=49934) which covers the things you need to do. Post# 7 of that summarises what you need to consider before writing off your device.

Cheers,

Alex

altera_forum · Answer

1) Yes, you are right. I connected pull-ups to 3.3V. But the voltage reference for Terasix blaster was connected correctly to 2.5V. I do not know, what i was thinking.

I have seen activity on both TDI and TMS. That is how i came to the conclusion, that JTAG on device might be fried. I expected to see some data on TDO, when TDI and TMS are active. I am glad to hear, that the TCK behaviour is normal. I was little worried, because i do not have acces to any evaluation board to have look at its TCK and the waveforms i found on the internet were looking pretty uniform.

One more thing comes to the mind: The TCK signal is not 2.5V as i would expect, but only 1.8V - 2V. I am not sure what voltage it exactly was, since i do not have access to my scope and the device at the moment. Is this normal behaviour?

Thank You for pointing me towards another thread!

Arnost

altera_forum · Answer

Hi,

I also just powered up my first own FPGA circuit last week (a Cyclone IV E), and I also had problems with JTAG in the beginning. In my case the nCONFIG pin was accidentally held low. This pin should be pulled high to VCCIO (not VCCA in this case) by 10k resistor. The handbook says that this pin causes the FPGA to reset, but it actually also disables JTAG. If you pull it low, the Quartus Programmer says "cannot access JTAG chain" or something like that. Now I did not put a scope to TDO, but I'd expect it to remain static if nCONFIG is low.

There's also the nCE pin which must be tied to GND for proper operation (except in a multi-FPGA configuration chain), but I don't know if pulling this pin high could cause the behaviour you describe.

Also, I agree with Alex that those devices are surprisingly tolerant against shorting pins in either direction. I don't have experiences with wrong voltages, though.

Best regards,

GooGooCluster

altera_forum · Answer

--- Quote Start ---

Beyond that the bare minimum you need to allow JTAG to work is:

nCE low.

nCONFIG pulled up.

nSTATUS pulled up.

MSEL pins connected to GND or VCCA (2.5V).

DCLK & DATA0 at valid levels.

Alex

--- Quote End ---

Could you please elaborate what valid levels of DCLK and DATA0 are? My DCLK and DATA0 go straight to the EPCS16 config. memory. Could this be a problem?

Thanks,

Arnost

altera_forum · Answer

Is the exposed pad of the FPGA properly connected to ground?

--- Quote Start ---

One more thing comes to the mind: The TCK signal is not 2.5V as i would expect, but only 1.8V - 2V. I am not sure what voltage it exactly was, since i do not have access to my scope and the device at the moment. Is this normal behaviour?

--- Quote End ---

This could indicate that the drivers in the USB blaster are fried. They are not very resilient and we had to change some several times. Do you have another working board that you can use to check if the USB blaster is working correctly?

--- Quote Start ---

Could you please elaborate what valid levels of DCLK and DATA0 are? My DCLK and DATA0 go straight to the EPCS16 config. memory. Could this be a problem?

--- Quote End ---

It should only be a problem if those pins are configured as inputs (i.e. with the MSEL pins in one of the "passive" configurations). But even in this case I don't think it should make the FPGA fail to answer on JTAG.

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Possible causes of dead cyclone IV on custom board

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