Forum Discussion
Altera_Forum
Honored Contributor
10 years agoIs the exposed pad of the FPGA properly connected to ground?
--- Quote Start --- One more thing comes to the mind: The TCK signal is not 2.5V as i would expect, but only 1.8V - 2V. I am not sure what voltage it exactly was, since i do not have access to my scope and the device at the moment. Is this normal behaviour? --- Quote End --- This could indicate that the drivers in the USB blaster are fried. They are not very resilient and we had to change some several times. Do you have another working board that you can use to check if the USB blaster is working correctly? --- Quote Start --- Could you please elaborate what valid levels of DCLK and DATA0 are? My DCLK and DATA0 go straight to the EPCS16 config. memory. Could this be a problem? --- Quote End --- It should only be a problem if those pins are configured as inputs (i.e. with the MSEL pins in one of the "passive" configurations). But even in this case I don't think it should make the FPGA fail to answer on JTAG.