Forum Discussion
Altera_Forum
Honored Contributor
10 years agoHi,
I also just powered up my first own FPGA circuit last week (a Cyclone IV E), and I also had problems with JTAG in the beginning. In my case the nCONFIG pin was accidentally held low. This pin should be pulled high to VCCIO (not VCCA in this case) by 10k resistor. The handbook says that this pin causes the FPGA to reset, but it actually also disables JTAG. If you pull it low, the Quartus Programmer says "cannot access JTAG chain" or something like that. Now I did not put a scope to TDO, but I'd expect it to remain static if nCONFIG is low. There's also the nCE pin which must be tied to GND for proper operation (except in a multi-FPGA configuration chain), but I don't know if pulling this pin high could cause the behaviour you describe. Also, I agree with Alex that those devices are surprisingly tolerant against shorting pins in either direction. I don't have experiences with wrong voltages, though. Best regards, GooGooCluster