Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Possible causes of dead cyclone IV on custom board

Hello, i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the han...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

Beyond that the bare minimum you need to allow JTAG to work is:

nCE low.

nCONFIG pulled up.

nSTATUS pulled up.

MSEL pins connected to GND or VCCA (2.5V).

DCLK & DATA0 at valid levels.

Alex

--- Quote End ---

Could you please elaborate what valid levels of DCLK and DATA0 are? My DCLK and DATA0 go straight to the EPCS16 config. memory. Could this be a problem?

Thanks,

Arnost