Forum Discussion
LukiLeu
New Contributor
New ContributorPorting of Ethernet Example Desgin from Arria 10 SX to Arria 10 GX Eval Board
I am currently trying to port the following Ethernet Example Design from the Arria 10 SX Eval Board to the Arria 10 GX Eval Board: https://www.intel.com/content/www/us/en/design-example/837384/arria-...
paveetirrasrie_Altera
Frequent Contributor
Frequent ContributorHello,
Apologies for the delayed response.
If you check the schematic, For ethernet connection pin, you may use Bank-3C. The schematic is attached in the devkit installer package. The clk is also located in Bank-3C. I'm referring to ARRIA 10GX SI Development Board. Are we align with this?
Regards,
Pavee
LukiLeuNew Contributor
New ContributorHi Pavee,
It seems we are not really moving forward with this issue...
As mentioned above we are using the following board: https://www.intel.de/content/www/de/de/products/details/fpga/development-kits/arria/10-gx.html
According to the schematic the pins are on Bank 3A:
