Honored ContributorHi,
I have designed Customised board using Cyclone V GX FPGA. I have fed 25MHz oscillator to non-dedicated clock pin in FPGA. So i had incorporated ALCLKCTRL. The design flow 25MHz -> altclkctrl ip -> altpll In this case pll not locked and therefore no pll output I have attached schematic file. Please support.https://alteraforum.com/forum/attachment.php?attachmentid=13877&stc=1
Honored ContributorReferring to the 'clock control block (altclkctrl) ip core user guide (https://www.altera.com/en_us/pdfs/literature/ug/ug_altclock.pdf)', only certain signals can drive the inclk port - those being:
--- Quote Start --- Clock pins, clock outputs from the PLL, and core signals can drive the inclk[] port. --- Quote End --- 'Ordinary' I/O pins cannot be connected to the ALTCLKCTRL inclk port. So, if your design ran through Quartus successfully, I suspect you've not got things connected up as you think - which may explain why the PLL isn't locking. Cheers, AlexHonored Contributorhi alex,
thanks for your reply. i can't figure out the thing why the pll is not locking. Have you refered those schematic files attached Is there anything wrong with schematics attached.Honored ContributorIf you must use a non-dedicated clock input pin, have you tried connecting to the PLL first instead of the clock control block? Why are you doing it in this order?
Honored ContributorYes - I looked at the bits of schematics you attached. The problem is, if you want to use a PLL, you're feeding your clock into the wrong pin. The PLL cannot be fed by that pin.
Using an ALTCLKCTRL block won't help as it can't be fed by a clock going into the pin you've chosen. This IP block should be fed by the output of a PLL, not the other way round. You need to modify the board to either: a) feed the clock into a dedicated clock pin; or b) add a wire loop on your board between an unused I/O pin and a dedicated clock pin and feed your clock signal out of that I/O pin so that the clock is fed to a dedicated clock pin. Cheers, Alex
