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Altera_Forum
Honored Contributor
9 years agoPLL is not working in Cylcone V GX (Using Integer PLL)
Hi, I have designed Customised board using Cyclone V GX FPGA. I have fed 25MHz oscillator to non-dedicated clock pin in FPGA. So i had incorporated ALCLKCTRL. The design flow 25MHz...
Altera_Forum
Honored Contributor
9 years agoYes - I looked at the bits of schematics you attached. The problem is, if you want to use a PLL, you're feeding your clock into the wrong pin. The PLL cannot be fed by that pin.
Using an ALTCLKCTRL block won't help as it can't be fed by a clock going into the pin you've chosen. This IP block should be fed by the output of a PLL, not the other way round. You need to modify the board to either: a) feed the clock into a dedicated clock pin; or b) add a wire loop on your board between an unused I/O pin and a dedicated clock pin and feed your clock signal out of that I/O pin so that the clock is fed to a dedicated clock pin. Cheers, Alex