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Altera_Forum
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8 years ago

PLL is not working in Cylcone V GX (Using Integer PLL)

Hi, I have designed Customised board using Cyclone V GX FPGA. I have fed 25MHz oscillator to non-dedicated clock pin in FPGA. So i had incorporated ALCLKCTRL. The design flow 25MHz...
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Altera_Forum
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8 years ago

Referring to the 'clock control block (altclkctrl) ip core user guide (https://www.altera.com/en_us/pdfs/literature/ug/ug_altclock.pdf)', only certain signals can drive the inclk port - those being:

--- Quote Start ---

Clock pins, clock outputs from the PLL, and core signals can drive the inclk[] port.

--- Quote End ---

'Ordinary' I/O pins cannot be connected to the ALTCLKCTRL inclk port. So, if your design ran through Quartus successfully, I suspect you've not got things connected up as you think - which may explain why the PLL isn't locking.

Cheers,

Alex