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Altera_Forum
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9 years ago

PLL is not working in Cylcone V GX (Using Integer PLL)

Hi, I have designed Customised board using Cyclone V GX FPGA. I have fed 25MHz oscillator to non-dedicated clock pin in FPGA. So i had incorporated ALCLKCTRL. The design flow 25MHz...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

hi alex,

thanks for your reply.

i can't figure out the thing why the pll is not locking.

Have you refered those schematic files attached

Is there anything wrong with schematics attached.