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Altera_Forum's avatar
Altera_Forum
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16 years ago

PLL comensate issue

Hi dears:

I am using ArriaGX devices. For some reason, the FPGA only has one input clock, which is input from one of the FPGA's transceiver reference clock pins. So when I implement pll in my project, there will be a warning information after compiling the project. The warning information is as below:

Warning: PLL "PLLDesign:inst|altpll:altpll_component|pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input.

My question is what caused this warning, and how to deal with it or how to compensate the pll's input clock?!

Thanks in advance!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The compensation is basically the idea that it's compensating from the clock input to the clock destination. This clock is recovered from a transceiver, and so the whole delay from the transceiver to the PLL is not compensated. Now, in your case that makes perfect sense and you really don't care. The warning is more for the person who brings the clock in on a pin that doesn't directly feed the PLL and thinks they'll get timing as if it were on a dedicated clock input that feeds the PLL. (For example, you get good Tco times. But in your case Tcos don't make sense by themself, since there is no true reference for the clock). Basically you can ignore this warning.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Rysc:

    Thanks for your reply.

    Are the transceiver (GXB) block's reference clock input pins not didecated clock pins? We know these pins supply ref clk for the GXB.

    Can you tell me what positon we need compenstation for the pll?!
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The PLL has a loopback path that it compensates for(generally this is one of the PLL clocks going through a global, and as one of its outputs, feeding back into the PLL). This is what it can compensate for. When you use a dedicated clk input pin, then the input to the PLL is a really quick path and has little affect on the overall clock delay(and can almost be accounted for with a phase-shift). So the net affect is your entire clock tree is compensated for, and it can be nicely correlated to the clock coming into the FPGA.

    When coming from a transceiver, there is some delay through the GXB and to the PLL that is not part of the loopback path and can't be compensated for. It can be calculated as a raw delay, but the PLL just won't be compensating for it over PVT. This is perfectly fine, as it's not like the recovered clock has some known reference edge that you need to relate to. In essence, it's physically impossible to compensate for the delay before the PLL, and that's perfectly fine in your design.

    (To think of where it would be useful, let's say you had two FPGA's recovering data. You couldn't synchronously pass data between the two recovered clocks, because they wouldn't be edge aligned. That's expected when recovering a clock and using it.) Hope that helps.